DAQ40 Software — User Guide

The common section contains generic parameters common to all DAQ links available on the host (both for AMC40 and PCIe40). ¶

Sets of parameters that describe the data format produced by a given TELL40 firware can be grouped under a dedicated section with a arbirary name (format is only a placeholder and can be customized). In simple cases with only one data format this section can be merged in the [common] section. ¶

Groups settings to be applied to a specific FPGA, as identified by its serial number in dashed form (the FPGA serial number can be found using pcie40_id, pcie40_daq and daq40_jtag). ¶

Groups settings to be applied to all FPGA devices in a given host, unless overridden by a device-specific setting. ¶

(AMC40 only) In order to configure an AMC40 setup, some additional sections in the configuration file are required. The first section is called [links] and it must contain a list of key-value pairs in the format: linkname=[on|off] where linkname is a dedicated section in the configuration file describing the configuration for a specific network interface. ¶

(PCIe40 only) Sections with this header configure a specific PCIe40 DAQ interface. XYZ refers to the interface name as specified in a [fpga:…​] section of the same configuration file and as reported by pcie40_id and pcie40_daq. If a setting is also specified in an [fpga:…​] section matching the same DAQ device, the latter takes precedence.

(PCIe40 only) If a name has not been specified for a PCIe interface, configuration parameters can still be assigned to it using a section name in this second form. The ? in the section name must be the integer corresponding to a PCIe interface number as reported by pcie40_id and pcie40_daq. ¶

(PCIe40 only) Whether to automatically reprogram a PCIe40 when PCIe communication issues are detected. Default value: true. ¶

Whether to check the integrity of the event ID sequence received on each stream. Default value: true.

Path of command used by pcie40_pgmserver to discover the JTAG topology available on the local machine and map it to the local PCIe topology. Default value: daq40_jtag ¶

If DIM publishing is enabled, controls the Dim Name Server to connect to (unless overridden by the -d command line argument to pcie40_pgmserver, pcie40_daqserver and amc40_daqserver, or by a device-specific or host-specific setting). Default value: this parameter is not set (uses DIM_DNS_NODE environment variable). ¶

If DIM publishing is enabled, controls what hostname a DIM server should use when announcing itself to the DIM Name Server (unless overridden by the DIM_HOST_NODE environment variable or by a device-specific or host-specific setting). Even if DIM support is disabled, setting this option (or the equivalent environment variable) always changes the hostname reported by gethostname(2) so that the two values always match. Default value: this parameter is not set (uses DIM_HOST_NODE environment variable). ¶

Arguments passed by pcie40_pgmserver to a GbtServ process. Default value: -level:0 ¶

Whether to keep the standard error stream open when pcie40_pgmserver starts a GbtServ process. Default value: false ¶

Whether to keep the standard output stream open when pcie40_pgmserver starts a GbtServ process. Default value: false ¶

Path of daemon controlled by pcie40_pgmserver to drive slow-control commands through a given PCIe40 board. Default value: GbtServ ¶

Time in seconds, after which pcie40_pgmserver will automatically restart a GbtServ process that died (a value of 0 disables the watchdog). Default value: 10 ¶

(PCIe40 only) JTAG clock frequency (in MHz). This value will be applied by pcie40_pgmserver when configuring all JTAG-connected FPGAs that do not explicitly override this value. Default value: 6. ¶

Controls the output of the local event builder. The following formats can be used:

Maximum size of the output file to write for a given DAQ link and for a given run. Once the given amount of data has been written, writing will stop and an error will be raised to the control system in order to avoid accidentally filling up the storage medium. Default value: 16384 (corresponding to 16 GiB). ¶

(PCIe40 only) The number of fragments referenced by each metadata block. Default value: 0 (meaning that the FPGA value will be left unchanged). ¶

Deterministic sampling interval at which data blocks are sent to the monitoring. Default value: 0 (meaning consecutive blocks will be posted to the monitoring buffer until full). ¶

Directory where to write fragment files with data received from the boards. Default value: /tmp. ¶

(PCIe40 only) Offset (in ps) used to align the external PLL of a given board after programming an FPGA with a fixed-latency firmware. Default value: 2000. ¶

(PCIe40 only) Path of command used by pcie40_pgmserver to align the external PLL of a given board after programming an FPGA with a fixed-latency firmware. Default value: pcie40_align_ext_plls. ¶

(PCIe40 only) Clock used to align the external PLL of a given board after programming an FPGA with a fixed-latency firmware. Default value: 1, where:

(PCIe40 only) Path of command used by pcie40_pgmserver to align the Phase Measurement PLL of a given board after programming an FPGA with a fixed-latency firmware. Default value: pcie40_align_pm_pll. ¶

(PCIe40 only) Path of command used by pcie40_pgmserver to calibrate the GBT banks of a given board after programming an FPGA. Default value: pcie40_calibrate_gbts. ¶

(PCIe40 only) Path of command used by pcie40_pgmserver to calibrate the phase measurement PLLs of a given board after programming an FPGA. Default value: pcie40_calibrate_pm_fplls. ¶

(PCIe40 only) Path of command used by pcie40_pgmserver to calibrate the SFP+ transceivers of a given board after programming an FPGA. Default value: pcie40_calibrate_tfcs. ¶

Arguments passed by pcie40_pgmserver to a pcie40_daqserver process. Default value: -m. ¶

(PCIe40 only) Path of daemon controlled by pcie40_pgmserver to drive the dataflow between the board and the host machine. Default value: pcie40_daqserver. ¶

(PCIe40 only) Time in seconds, after which pcie40_pgmserver will automatically restart a pcie40_daqserver process that died (a value of 0 disables the watchdog). Default value: 10. ¶

Extra arguments passed by pcie40_pgmserver to a {pcie40_llimon} process. Default value: empty. ¶

Whether to keep the standard error stream open when pcie40_pgmserver starts a pcie40_llimon process. Default value: false ¶

Whether to keep the standard output stream open when pcie40_pgmserver starts a pcie40_llimon process. Default value: false ¶

(PCIe40 only) Path of daemon controlled by pcie40_pgmserver to monitor the status of the LLI on a given board. Default value: /opt/lhcb/p40-lli-devices/SCRIPTS_FC0/TOOLS/p40_llimon/pcie40_llimon.py. ¶

(PCIe40 only) Time in seconds, after which pcie40_pgmserver will automatically restart a pcie40_llimon process that died (a value of 0 disables the watchdog). Default value: 10. ¶

(PCIe40 only) Path of daemon controlled by pcie40_pgmserver to drive the local event builder. Default value: "". ¶

(PCIe40 only) Time in seconds, after which pcie40_pgmserver will automatically restart a pcie40_localebserver process that died (a value of 0 disables the watchdog). Default value: 10. ¶

(PCIe40 only) Path of command used by pcie40_pgmserver to configure the external PLLs of a given board after programming an FPGA. Default value: pcie40_program_ext_plls. ¶

(PCIe40 only) Path of command used by pcie40_pgmserver to reinitialize the PCIe link after programming an FPGA. Default value: pcie40_reload. ¶

(PCIe40 only) Hostname where pcie40_daqserver should submit metrics. Default value: "". ¶

(PCIe40 only) Port where pcie40_daqserver should submit metrics. Assumes a telegraf http_listener_v2 input accepting influx line protocol metrics under the /telegraf endpoint. Default value: 8086. ¶

Folder used to store runtime files, like PID files and the command FIFOs. Default value: /run/. ¶

Directories to be searched, in order, for FPGA firmware images specified using relative paths. Multiple paths can be separated by colons. Default value: /opt/lhcb/daq40/firmware/merge:/opt/lhcb/daq40/firmware/nightly:/opt/lhcb/daq40/firmware ¶

If a file was generated with a fixed TFC prescale factor to limit the output bandwidth (for example from an RTL simulation), this feature should be enabled and the next two parameters should be set accordingly. Default value: false. ¶

If tfc_prescale_enable is true, this sets the interval between consecutive accepted BXIDs. Default value: 1 (meaning no BXIDs are skipped). ¶

If tfc_prescale_enable is true, this sets the first BXID output by the TFC. Default value: 0 (meaning no BXIDs are skipped at the start of run). ¶

(AMC40 only) Number of udp packet buffers to preallocate for each network link. Default value: 100000. ¶

When pcie40_pgmserver detects that a monitored process has died, it will wait a configurable timeout before attempting to restart it. If the restart fails, it will keep trying at exponentially longer intervals. This parameter sets the upper limit, in seconds, for this exponential backoff. Default value: 300 (5 minutes) ¶

Whether the Data Processing module on the readout board will keep the BXID in each optical input link before outputting a fragment. Default value: false (as this is redundant information that is already available in the global fragment header). ¶

Size, in bits, of the BXID counter sent from the front-end (except for sync frames where it’s always 12). Default value: 12. ¶

Size, in bits, of each channel received from a given optical input link. Default value: 4. ¶

Whether the data length field is present in every header transmitted by the front-end. Default value: false.

Size, in bits, of the data length field in the front-end header, if present. Default value: 7.

Decimal or hexadecimal bitmask describing which input links are enabled for data acquisition. Default value: 0. ¶

A string, in scanf(3) format, used to locate frontend input files. Default value: "". ¶

Possible values are upstream, scifi, calo, muon, rich or velo. Default value: "". ¶

Size, in bits, of frames received from each fron-end optical input link. Default value: 80 (corresponding to a standard GBT protocols, other valid values are 112 for WideBus and 128 for GWT). ¶

Whether the header is on the most or least significant side of the frame. Default value: false (meaning header is on lsb side, this is however a legacy setting and all modern firmware configurations should be msb). ¶

Size, in bits, of the additional info field seen after the BXID in the header. Default value: 1 (meaning only the nodata bit is present). ¶

Position of the nodata bit relative to the beginning of the front-end header. Default value: fe_bxid_bits (meaning the first bit right after the BXID). ¶

Total number of bits transmitted over a front-end link in response to an NZS command. Default value: fe_channel_bits*fe_nzs_channels. ¶

Total number of channels transmitted over a front-end link in response to an NZS command. Default value: 128. ¶

Size, in bits, of the sync pattern to look for. Default value: fe_frame_bits-fe_bxid_bits ¶

Bit pattern used to detect synchronization frames from the front-end. Its size should be fe_sync_bits. ¶

Given a VeloPix chip id N, specifies (as a comma-separated list of integers) which optical links are connected to that chip. ¶

Whether to enable the external LHC clock input. Default value: false. Valid in sections: fpga, pcie, host, common. ¶

Overrides the clock type that is automatically detected from the FPGA firmware. Refer to the PCIe40 clocks appendix for more information and the list of accepted values. Valid in sections: fpga, pcie, host, common. ¶

Overrides the DIM DNS node to be used for communication between the control system and the given FPGA. Default value: no override. Valid in sections: fpga, pcie, host, common. ¶

Overrides what hostname a DIM server should use when announcing itself to the DIM Name Server. Setting this option always also changes the hostname reported by gethostname(2) so that the two values always match. Default value: no override. Valid in sections: fpga, pcie, host, common. ¶

Whether this FPGA is to be managed by pcie40_pgmserver and pcie40_daqserver. Default value: true. Valid in sections: fpga, pcie, host, common. ¶

(PCIe40 only) For pcie40_pgmserver, controls whether to monitor link failures and driver reloads on the first (:0) and second (:1) PCIe link on the given FPGA. For pcie40_daqserver, controls whether to use this PCIe interface for DAQ. Default value: the boolean value of the enabled parameter for this FPGA. Valid in sections: fpga, pcie, host, common.

JTAG clock frequency (in MHz). This value will be applied by pcie40_pgmserver when configuring the given FPGA. Default value: 6. Valid in sections: fpga, pcie, host, common. ¶

Whether the JTAG chain is jumpered to only expose the FPGA (bypassing the onboard CPLD). Default value: false. Valid in sections: fpga, pcie, host, common. ¶

Whether to enable the main DAQ stream on a given PCIe40 interface. Default value: true. Valid in sections: fpga, pcie, host, common. ¶

Controls how to output the data fragments received from this PCIe interface. The following formats can be used:

Whether to enable or not the meta DAQ stream on a given PCIe40 interface. If false, data fragments from this interface (both in the main and the odin streams) will be written in host memory in their original format. If true, data fragments will be internally packed and reformatted according to the MFP data format while being written to host memory. Default value: false. ¶

Sets the human-readable name for this board. Both interfaces will have the same name but they can still be distinguished by their numerical link identifier. Valid in sections: fpga.

The configuration key name:0 sets the human-readable name for the first PCIe link of a given board, and name:1 for the second. The name is an ASCII string consisting of up to 8 characters. This parameter, if present, takes precedence over name (without the colon). Valid in sections: fpga.

Whether to enable the odin DAQ stream on a given PCIe40 interface. Default value: false. Valid in sections: fpga, pcie, host, common. ¶

Whether to enable the odin DAQ stream on a given PCIe40 interface. Default value: false. Valid in sections: fpga, pcie, host, common. ¶

Controls how to output the ODIN banks received from a specific interface. The format of this option is analoguous to the main_out option. ¶

Path to .sof file to be programmed into FPGA. Paths starting with a slash are considered absolute. Paths that do not are considered relative to the directories specified under the sof_search_dirs common setting (each directory will be tried in order until a .sof file is found). Valid in sections: fpga, pcie, host, common. ¶

Source identifier assigned to this interface (0 or 1 configure the source id for the first or the second TELL40, respectively). This 16-bit number is unique throughout the experiment and encodes both which subdetector and what slice of the subdetector is connected to each data source. Default value: PCIe interface number. Valid in sections: fpga, pcie, host, common.

The truncation threshold (in number of words), the DMA controller will assert backpressure when the input buffer fills above this value. Default value: 0 (meaning that the FPGA value will be left unchanged). Valid in sections: fpga, pcie, host, common. ¶

The name of the network device to configure as it appears in ifconfig or ip. ¶

The IPv4 address, in dotted decimal format, of the destination interface (on the PC) where the AMC40 is to transmit data.

Examine WinCC project winccproj. In addition to checking operating system configuration the tool will also check the WinCC OA components that were installed in the given project. This option can be used at most once (that is, if you are running several projects, only give the one you are working on at the moment). ¶

Use output as file name for final report. If not given a default name will be generated using the current hostname and time. ¶

Display a short synopsys. ¶

Use given JTAG cable interface. jtagcable is an integer as printed by quartus_pgm -l. By default all cables are enumerated (see also the -a option). ¶

Query all available JTAG cable interfaces (this is the default behaviour). ¶

Use given JTAG clock frequency. mhz is an integer between 6 (the default value) and 24. ¶

Dump build-id. When this option is used, the build-id ROM contents (describing build environment and version control status) will be decoded and printed. ¶

Dump PCIe link training information. When this option is used, PCIe LTSSM logs will be decoded and printed. ¶

Reset PCIe interface (0 or 1) over JTAG. ¶

SOF scan. When this option is used, .sof files will be scanned to perform usercode identification. ¶

Produce INI output. This setting changes the output to a format that can be easily parsed by other programs. ¶

Extract the user code from the given .sof file and print it. ¶

Path to a .sof file or to a directory containing .sof files. If given, the tool will try to derive the JTAG usercode from the .sof files and match it against what is stored in the FPGA. The option can be repeated to include more paths in the search. By default only the paths /opt/lhcb/daq40/firmware and ~/sof_files are searched. ¶

The path to the Quartus installation to use. If defined, the signaltap binary must be located at ${QUARTUS_ROOTDIR}/bin/quartus_stp. ¶

Increase output verbosity. ¶

Parse given configuration file. Repeat to use more. ¶

Initial event ID to be analyzed (previous ones will be skipped). ¶

Load all front-end input data files from txtdir directory. The individual files will be located automatically.

Load front-end input data from file.txt. In this form this option should be repeated for each front-end input link used. ¶

Respectively enable or disable verbose output. In the first mode (the default), an hexadecimal dump of each fragment is displayed. In the second mode only an aggregate summary about the Event ID sequence in the file is displayed. ¶

Number of rows to use when displaying hexadecimal payload data. This option defaults to 32. ¶

Instead of printing raw hexadecimal data, use format parameters from cfgfile to decode the fragment contents. ¶

Take decoding parameters from decodekey section of configuration file.

Output short program synopsis and exit. ¶

Number of rows to use when displaying hexadecimal payload data. This option defaults to 32. ¶

Instead of printing raw hexadecimal data, use format parameters from cfgfile to decode the fragment contents. ¶

Respectively enable or disable verbose output. ¶

First event ID override. Only useful in case fragment data starts with an event ID other than 0. ¶

Source ID override, this option can be repeated between .frg file arguments to assign different source IDs to different input files. Input files without an explicit source ID automatically use the source ID of the previous file, increased by 1. A value of 0 (the default) will just copy the source_id field of the .frg file header. Accepts a number in hexadecimal, decimal or octal format as specified by strtoul(3). ¶

Raw bank type to use in MDF file for non-ODIN banks, this option can be repeated between .frg file arguments to assign different bank types to different input files (the last specified type will be applied to all following inputs on the command line). Accepts a number in hexadecimal, decimal or octal format as specified by strtoul(3).

Path where to write output in MDF format (use '-' as argument to write to standard output). ¶

Output short program synopsis and exit. ¶

Increase output verbosity. ¶

Parse given configuration file. Repeat to use more. ¶

Source ID to be analyzed as a decimal or hexadecimal number (an MDF file usually contains data from several sources). ¶

Initial event ID to be analyzed (previous ones will be skipped). ¶

Load all front-end input data files from txtdir directory. The individual files will be located automatically.

Load front-end input data from file.txt. In this form this option should be repeated for each front-end input link used. ¶

Respectively enable or disable verbose output. In the first mode (the default), an hexadecimal dump of each bank payload is displayed. In the second mode only header information is displayed. ¶

Number of rows to use when displaying hexadecimal payload data. This option defaults to 32. ¶

Output short program synopsis and exit. ¶

Path to a text file describing the bank type remapping to be performed (according to the format described below). Default value: /opt/lhcb/daq40/mdfvalidator.map. ¶

Path to .mdf file containing the converted output. If a file at this path already exists it will be overwritten. Default value: <inputpath>_valid.<inputextension>. ¶

A bank type from the input .mdf file. This is a numerical value expressed in either decimal or hexadecimal format.

The bank type to be emitted in the output file when a bank of type type_in is found in the input file. Supports the same format as type_in, in addition can be specified as a (case-insensitive) string containing the full name of the raw bank type to produce.

Load cfgfile. The option can eventually be repeated to load parameters from multiple configuration files. ¶

Take decoding parameters from section decodesec in the configuration file. These parameters should of course match the subdetector constants used to configure the firmware when these files were generated. Refer to the configuration file format documentation in order to set these parameters. Load decoding Default value: common. ¶

Take binary front-end data from inputfile. Each line in the file represents one frame of front-end data followed by a single digit representing the datavalid bit for the same frame. ¶

Create ramdisk at path. Path will be created if it does not exist. By default the ramdisk will be created at /tmp/daq40_ramdisk. ¶

Size of ramdisk. Use an M or G suffix to specify if the given quantity is in MegaBytes or GigaBytes. By default 2G will be allocated.

List all the WinCC project registered and runnable on the machine. The output includes the project name, path, timestamp and current status. ¶

List WinCC information (project name, path, timestamp and current status) for the given project. ¶

Creates an empty WinCC project at the specified path and registers it with WinCC. ¶

Starts the given WinCC project (or all the projects if no argument is given). ¶

Restarts the given WinCC project (or all the projects if no argument is given). ¶

Launches GEDI within the given WinCC project. ¶

Launches DeviceEditorNavigator within the given WinCC project. ¶

Tail all logs from the given WinCC project. ¶

Without arguments, lists the components available to be installed on the local system. With an argument, reports the components installed in the given WinCC project (the project must already be running). ¶

Installs the specifed component, or components, inside the given WinCC project. For each component, the path to the corresponding XML manifest file should be specified. ¶

Stops the given WinCC project (or all the projects if no argument is given). ¶

Deletes the given project from WinCC, the project should be stopped before attempting this operation. The project files are not deleted and will remain at their previous location, so that the project can be registered again inside the WinCC Project Administrator if needed. ¶

Path to WinCC installation, usually /opt/WinCC_OA/3.16 ¶

Select PCIe40 interface to access. The interface can be specified either by its number, its name, or its FPGA serial code. This is optional and by default the tool will bind to the first interface available (typically 0). ¶

Access BAR number bar. Two PCI BARs are available:

Address to use for BAR access. Can be in decimal, hexadecimal or any other format supported by strtol(3). ¶

Register name on the given BAR. Only top-level register names are currently supported. Refer to the BAR0 PCIe register map appendix of the developer guide for the full list. ¶

Write 32-bit value to register at the given address. Same input format considerations apply as for the -a option. ¶

Read value of register at given address. Value is printed to stdout in hexadecimal format. ¶

Resize BAR (applies to reverse BARs only). ¶

Benchmark mode (repeat same read or write operation until stopped and calculate frequency every second). ¶

Output short program synopsis and exit. ¶

Enable verbose mode. Any error message will be printed to stderr. ¶

Output short program synopsis and exit. ¶

Select PCIe40 interface to access, either the interface number or its name can be used. Can be repeated to control multiple interfaces. By default all detected interfaces are accessed. ¶

Display interface status. This is the default command if no options are given. Can be repeated in a command sequence in order to see the interface status after a given intermediate command in the sequence. ¶

Enable or disable verbose output. ¶

Perform a reset of the selected DMA interface. Four reset modes are available:

Configure the input buffer threshold above which backpressure is asserted. ¶

Respectively enable or disable the selected DMA stream. Possible values:

Respectively enable or disable the embedded data generator to test the main (by default) or odin (if selected using -s first) DMA streams. ¶

Respectively start or stop the embedded data generator to test the main DMA stream. For data to be generated, the buffers must not be full and the generator must be both enabled and running. An enabled generator can be stopped and started several times to manually observe the buffering behaviour. To control the odin stream generator instead, first select that stream using -s. ¶

Configure the generator to respectively emit pseudo-fragments or a fixed pattern. The first mode allows testing the metadata acceleration and the fragment sequence integrity. The second allows testing the downstream data integrity across the PCIe link. ¶

Set rate limit of generator (0 = no limit, 100 = no data). ¶

Start the data integrity checker (interface must have previously been put into pattern generation mode with -F). The check will continue indefinitely or until the next wait timeout (see -w). ¶

In the first mode, output the contents of the selected DMA stream buffer to file (to write to standard output use - for the file argument). In the second, immediately discard the buffered data and just measure the DMA throughput. ¶

Exit after processing mibs MiBs of data (to be used with -o or -c). ¶

Sets the metadata packing factor to the given mpf (integer) value. ¶

Poll last selected stream continuously every ms milliseconds. ¶

Scrub (overwrite with zeros) the DMA buffers of the last selected stream. ¶

Examine DMA buffers of the last selected stream. ¶

Sleep for millis milliseconds before executing the next command in the command line sequence. ¶

Load configuration file. See also daq40.cfg. ¶

Run in debug mode. In this mode every enabled DMA stream must be filled with known test patterns that the software can verify. ¶

Overrides the default DIM_DNS_NODE. For debugging, DIM publication and subscription can be completely disabled using -D. ¶

Output short program synopsis and exit. ¶

Bind to PCIe40 interface interface, the argument can be either an interface number, interface name or common board name. This is not optional only when using -D. The option can be repeated to use multiple interfaces. ¶ If -i is specified at least once, the top-level FSM controller is not instantiated (the WinCC FSM will manage each interface individually). If -i is not specified, all interfaces detected on the current host will be used and a common top-level FSM will be instantiated (for backwards compatibility with MiniDAQ2 setups). ¶

Run in monitor mode. In this mode no new settings will be applied to the PCIe40 devices (as that is delegated to the Control System), the program will only monitor device state. ¶

Override the default location for data files ( /tmp unless changed by the configuration file). For debugging, the creation of data files can be inhibited using -O. ¶

Reset the PCIe core on the FPGA to its default state when the server starts. By default no reset is sent (this is equivalent to starting with -R) but this behaviour can be toggled by -r. ¶

Increase verbosity. Option can be repeated multiple times. ¶

Decrease verbosity. Option can be repeated multiple times. ¶

If DIM is enabled, overrides the local hostname announced to the DIM Name Server. ¶

If DIM is enabled, specifies the DIM Name Server to use for publications and subscriptions. -d overrides this value. ¶

Load configuration file. See also daq40.cfg. ¶

Overrides the default DIM_DNS_NODE. For debugging, DIM publication and subscription can be completely disabled using -D. ¶

Output short program synopsis and exit. ¶

Override the default location for data files ( /tmp unless changed by the configuration file). For debugging, the creation of data files can be inhibited using -O. ¶

If DIM is enabled, overrides the local hostname announced to the DIM Name Server. ¶

If DIM is enabled, specifies the DIM Name Server to use for publications and subscriptions. -d overrides this value. ¶

Select PCIe40 interface to use. The interface can be specified either by its number, its name, or its FPGA serial code. If omitted, all interfaces will be used. ¶

Controls the LEDs identifying the given interface. The argument can have the following values:

Sets the name of the given interface. The name is an ASCII string of up to 8 characters (any extra characters will be ignored). This identification string is supposed to be unique within the entire system.

Sets the unique source identifier of the given interface. The ID is a 16-bit number unique within the entire system.

Dumps the build ROM contents used to indentify the FPGA firmware. Only link 0 of each board supports this command and it is ignored on link 1. ¶

Dumps the EEPROM contents used to identify a specific board. Only link 0 of each board supports this command and it is ignored on link 1.

Apply command to all boards known to the local pcie40_pgmserver process. ¶

Reprogram the last firmware programmed by pcie40_pgmserver on the given board. Requires -n. ¶

Run directory used by pcie40_pgmserver. Only required if using -n and only to override the automatically detected path. Default value: /run/. ¶

Name of board to be programmed. boardname is the name as it appears in the daq40.cfg configuration file. In order to use this option, the pcie40_pgmserver daemon must be running. ¶

Use given JTAG cable interface. jtagcable is an integer as printed by quartus_pgm -l. The default value is 1. This option can be repeated to program multiple boards at once (sequentially). ¶

Use given JTAG clock frequency. mhz is an integer between 6 and 24. This option can be used also without giving a programming file in which case it will just set the JTAG clock frequency and exit.

Configure JTAG chain with only a single device. This option is to be used if the MAX5 has been hidden from the JTAG chain via physical DIP switch. Only .sof files are compatible with this mode. ¶

Using a single dot as the firmware path argument triggers special behaviour, in this case the last SOF file loaded on the FPGA will be programmed again.

The SRAM Object File file to program on the PCIe40 FPGA. ¶

The Programmer Object File file to store on the PCIe40 flash memory. ¶

The path to the Quartus installation to use. If defined, the programmer binary must be located at ${QUARTUS_ROOTDIR}/bin/quartus_pgm. ¶

Load configuration file. See also daq40.cfg. ¶

Output short program synopsis and exit. ¶

Overrides the default DIM_DNS_NODE. For debugging, DIM publication and subscription can be completely disabled using -D. ¶

If DIM is enabled, overrides the local hostname announced to the DIM Name Server. ¶

If DIM is enabled, specifies the DIM Name Server to use for publications and subscriptions. -d overrides this value. ¶

Resets and reconfigures the program. Can be used after editing the configuration file in order to cleanly apply the new configuration, without killing the process. ¶

Cleanly terminates all managed processes and ultimately exits the program itself. ¶

Remove and then re-insert module into kernel (this is required after a driver update). ¶

Reload all interface (by default only the interfaces where the FPGA has been reprogrammed are reloaded). ¶

Take the device list from the local cache, if it exists. By default the cache is used only if it contains more entries than what are currently detected in the system. With this option the cache contents are used regardless. ¶

Forces a cache update. By default the cache is updated only if additional entries have been detected compared to the current cache contents. With this option the cache will be overwritten regardless. ¶

Suppress dmesg output. Without this option a partial dmesg log is printed for troubleshooting in case of errors. ¶

Attempt to hard-reset the given endpoint. Sometimes this can help to recover a failed PCIe link, but this can also break an otherwise functioning link, only try when no other options are left! ¶

Print a short help message. ¶

Install systemd units for both jtagd and pcie40_pgmserver.

Start (or restart) systemd units installed by -i. ¶

Reload configuration of pcie40_pgmserver. ¶

Stop systemd units installed by -i. ¶

Display status of systemd units installed by -i (this is the default action if no option is specified). ¶

Display (and follow) log of systemd units installed by -i.

Uninstall the systemd units installed by -i. The corresponding services will first be stopped. ¶

If this environment variable is set when issuing the pcie40_systemd -i command, its value will be captured and stored in the environment of the pcie40_pgmserver service. If this environment variable is not set, the installation will use the value read from /etc/sysconfig/dim. ¶

If this environment variable is set when issuing the pcie40_systemd -i command, its value will be captured and stored in the environment of the pcie40_pgmserver service. ¶

Contains environment variables used by pcie40_pgmserver and its children processes. This file is overwritten by package updates and it should not be modified.

Contains local customizations to the settings and environment variables used by pcie40_pgmserver and its children processes. ¶

Respectively enable or disable verbose output. In the first mode (the default), an hexadecimal dump of each fragment is displayed. In the second mode only an aggregate summary about the Event ID sequence in the file is displayed. ¶

Number of rows to use when displaying hexadecimal payload data. This option defaults to 32. ¶

Output short program synopsis and exit. ¶

Limit conversion only to first limit fragments. Default value: 0 (meaning no limit). ¶

Path to .frg file where to store converted output. If a file at this path already exists it will be overwritten. Default value: <inputbasename>.frg. ¶

Increase output verbosity. ¶

Parse given configuration file. Repeat to use more. ¶

Load SuperODIN banks from file.frgsim. ¶

Load simulation output from file.frgsim. ¶

Load all front-end input data files from txtdir directory. The individual files will be located automatically.

Load front-end input data from file.txt. In this form this option should be repeated for each front-end input link used. ¶

Respectively enable or disable verbose output. In the first mode (the default), an hexadecimal dump of each fragment is displayed. In the second mode only an aggregate summary about the Event ID sequence in the file is displayed. ¶

Number of rows to use when displaying hexadecimal payload data. This option defaults to 32. ¶

Output short program synopsis and exit. ¶

Load parameters from cfgfile. This parameter is optional and it defaults to daq40.cfg. ¶

Only configure the given link (identified by its section name in the configuration file). If all is given (the default) then configure all the links that are enabled in the [links] section of the configuration file. ¶

Overrides the default location of the main configuration file. ¶

Increase output verbosity. ¶

Parse given configuration file. Repeat to use more. By default only daq40.cfg is parsed. ¶

Take decoding parameters from configuration file section named decodesec. Default value: common. ¶

Load front-end input data from file.txt. Repeat this option for each front-end input link used, in increasing link number order. ¶

PCAP file (or files) to be analyzed. ¶

Enable verbose mode. In verbose mode the reception of a packet will be marked by printing an 'X' character to the console, likewise, the loss of packets will be marked by a dot. ¶

Listen for UDP data on udpport. If a configuration file is specified, this value is ignored. ¶

Load network parameters from cfgfile. This program will look for a section named 'mep_0' and will use the 'udp_dst' and 'ip4_dst' parameters from there. ¶

Write files to directory outdir. The current working directory is used by default. ¶

Limit size of output file to maxmbytes MiBs. By default a 1 GiB limit is enforced. ¶

Load configuration file. See also daq40.cfg. ¶

Bind to AMC40 network interface associated with link. This is not optional only when using -D. Option can be repeated to use multiple links. By default all links that are enabled in the configuration file are used. ¶

Overrides the default DIM_DNS_NODE. For debugging, DIM publication and subscription can be completely disabled using -D. ¶

Output short program synopsis and exit. ¶

If DIM is enabled, overrides the local hostname announced to the DIM Name Server. ¶

If DIM is enabled, specifies the DIM Name Server to use for publications and subscriptions. -d overrides this value. ¶

Use given JTAG cable interface. jtagcable is an integer as printed by quartus_pgm -l. The default value is 1. ¶

The SRAM Object File file to program on the AMC40 FPGA. ¶

The path to the Quartus installation to use. If defined, the programmer binary must be located at ${QUARTUS_ROOTDIR}/bin/quartus_pgm. ¶

Configuration file to load network parameters for a given 10G link. Default value: /etc/daq40.cfg. ¶

Generate fragments at a rate of ratekhz. Default value: 100000. ¶

Make all generated fragments of size fragbytes. Default value: 100. ¶

Assume the Ethernet MTU to be ethmtu bytes when determining the maximum block size to transmit. Default value: 9000. ¶

Enable data generation on network link link (as specified in the configuration file). This option can be repeated to enable more links.

Amount of memory (in MiBs) to allocate for each main stream circular buffer. The driver will try to allocate this much memory but the final DMA buffer might be smaller in case of memory pressure from the DMA allocator. The default value is 4096. For versions up to 6.1 this is also the maximum value. Later versions built with HUGEPAGES_SUPPORT can use up to 1073741824 MiBs (1 TiB) but will default to 32 GiB. ¶

Amount of memory (in MiBs) to allocate for each odin stream circular buffer. The default value is 1024. SODIN firmwares support up to 4096 until version 6.1 and up to 1073741824 on later versions built with HUGEPAGES_SUPPORT. ¶

Explicit NUMA bindings for DMA buffer allocation. The parameter is a comma-separated list where a given PCIe interface is identified by its topological Bus:Device.Function address. ¶

VMA flags to apply to DMA buffers. Possible values are:

Size (in MiBs) of huge memory pages used for DMA buffers. Requires a driver compiled with HUGEPAGES_SUPPORT. Default value is 0 (which disables hugepages). Acceptable values depend on what the specific architecture supports. The maximum is 1024 (1 GiB). ¶

Whether to automatically attempt a PCIe link retrain on PCIe40 devices with a degraded PCIe link state. The default value is true. ¶

Whether to allow relaxed TLP ordering on PCIe40 endpoints. The default value is true. ¶

Device to access user registers on the FPGA. ¶

Device to access low-level registers on the FPGA. ¶

Device to access the DMA controller. ¶

Device to access the main DMA stream. ¶

Device to access the meta DMA stream. ¶

Device to access the odin DMA stream (where X is between 0 and 4). ¶

In order to change the default module parameters, create a file at this path, containing a line like the following: ¶

Information about the DMA pseudo-filesystem. ¶

Global source identifier for this PCIe40 interface, this value uniquely identifies a PCIe40 interface throughout the entire readout system. ¶

Driver build version. For packaged drivers it will match the version and release identifiers of the package. For manually built drivers il will be the string "local-wip". ¶

Driver register map identifier. This value is checked to ensure the driver and the FPGA use the same register definitions. ¶

PCIe core version. This value is checked to ensure compatibility between driver and the FPGA. ¶

PCIe link training state machine log. ¶

Local link number identifying this interface within one PCIe40 board (0 for the primary and 1 for the secondary). ¶

Dynamic interface number allocated by the driver, this value uniquely identifies a PCIe40 interface within the machine until the next pcie40_reload. ¶

1 if the FPGA BARs are readable, 0 if the FPGA has been reprogrammed and the driver must be reloaded. ¶

Space-delimited list of all PIDs currently accessing this interface. ¶

Trigger a retrain of the PCIe link by writing the desired link configuration to this attribute file. The configuration is a string in the format "genN" with N being a number between 0 and 4 (the "gen" prefix is optional). A value of 0 is equivalent to requesting the highest speed the endpoint is capable of. ¶

Amount of memory (in MiBs) to allocate for each main stream circular buffer. The driver will try to allocate this much memory but the final DMA buffer might be smaller in case of memory pressure from the DMA allocator. The default value is 4096. For versions up to 6.1 this is also the maximum value. Later versions built with HUGEPAGES_SUPPORT can use up to 1073741824 MiBs (1 TiB) but will default to 32 GiB. ¶

Amount of memory (in MiBs) to allocate for each odin stream circular buffer. The default value is 1024. SODIN firmwares support up to 4096 until version 6.1 and up to 1073741824 on later versions built with HUGEPAGES_SUPPORT. ¶

Explicit NUMA bindings for DMA buffer allocation. The parameter is a comma-separated list where a given PCIe interface is identified by its topological Bus:Device.Function address. ¶

VMA flags to apply to DMA buffers. Possible values are:

Size (in MiBs) of huge memory pages used for DMA buffers. Requires a driver compiled with HUGEPAGES_SUPPORT. Default value is 0 (which disables hugepages). Acceptable values depend on what the specific architecture supports. The maximum is 1024 (1 GiB). ¶

Whether to automatically attempt a PCIe link retrain on PCIe40 devices with a degraded PCIe link state. The default value is true. ¶

Whether to allow relaxed TLP ordering on PCIe40 endpoints. The default value is true. ¶

First interface number for emulated boards (0 by default, increase to avoid conflicts with real boards already detected in the machine). ¶

Number of PCIe40 boards to emulate (1 by default). Two DAQ interfaces will be instantiated for each emulated board. ¶

Packing factor for metadata blocks (10000 by default). ¶

Device to access user registers on the FPGA. ¶

Device to access low-level registers on the FPGA. ¶

Device to access the DMA controller. ¶

Device to access the main DMA stream. ¶

Device to access the meta DMA stream. ¶

Device to access the odin DMA stream (where X is between 0 and 4). ¶

In order to change the default module parameters, create a file at this path, containing a line like the following: ¶